1. Field of the Invention
The present invention relates to a solid state image sensing device, and more particularly, it relates to the structure of regions for controlling reading of signal charges in a solid state image sensing device employing charge-coupled devices as means for reading the signal charges.
2. Description of the Prior Art
A solid state image sensing device is provided with photoelement arrays formed by a number of photodiodes or the like to sequentially read signal charges stored in the respective photoelements in response to the amount of incident light thereby to extract picture signals. For example, "An Interline-Transfer CCD Imager with Floating Photodiodes" by S. Miyatake et al., IEDM "Digest of Technical Papers" 1980, pp. 342-345 discloses a solid state image sensing device which controls transfer gates and gates of CCDs by common gate electrodes
FIG. 1 is a sectional view showing a single cell of a conventional solid state image sensing device of an interline transfer system, and FIGS. 1A and 1B are potential diagrams thereof. Referring to FIG. 1, description is now made on the structure of the conventional sold state image sensing device. In the solid state image sensing device of the interline transfer system, photosensitive parts are formed by photodiodes, MOS transistors or the like, while storage parts are formed by charge-coupled devices (CCDs) vertically aligned in a parallel manner to the photosensitive parts.
Referring to FIG. 1, a single cell of the solid state image sensing device includes a semiconductor substrate 1, isolation regions 2 prepared by highly concentrated impurity regions identical in conductivity type to the semiconductor substrate 1, buried channel type vertical CCDs formed by impurity regions 3 different in conductivity type from the semiconductor substrate 1, transfer gates formed by ion implantation layers 4 identical in conductivity type to the semiconductor substrate 1, gate electrodes 5 for the vertical CCDs, shielding films 6 for preventing light from entering the vertical CCDs, photodetectors 70 formed by PN junction of the semiconductor substrate 1 and highly concentrated impurity regions 7 different in conductivity type from the semiconductor substrate 1 and an insulator film 9 provided on the semiconductor substrate 1.
Description is now briefly made on a method of manufacturing the conventional solid state image sensing device as shown in FIG. 1.
The isolation regions 2 are first formed in the semiconductor substrate 1. Then the buried channels 3 are formed in the surface layer of the semiconductor substrate 1 in portions adjacent to the isolation regions 2. Thereafter the transfer gates 4 are formed in the surface layer of the semiconductor substrate 1 in portions adjacent to the buried channels 3. Then an insulator film 9 is formed on the surface of the semiconductor substrate 1. Thereafter the gate electrodes 5 are formed on the insulator film 9 to cover the isolation regions 2, the buried channels 3 and the transfer gates 4. The gate electrodes 5 are formed through use of masks, which are so correctly registered as to align the edge 51 of each gate electrode 5 as formed with the edge 41 of each transfer gate 4. Then ion implantation is performed by utilizing the gate electrodes 5 as masks, to form the impurity regions 7. Thereafter the insulator film 9 is formed on the gate electrodes 5, an finally the shielding films 6 are formed on the same.
With reference to FIGS. 1, 1A and 1B, description is now made on the operation of the conventional solid state image sensing device. FIG. 1A shows a state of storing signal charges and FIG. 1B shows a state of reading the signal charges. In the state as shown in FIG. 1A, the transfer gates 4 and the gates of the vertical CCDs are controlled by common gate electrodes 5, and in response to clock signals .phi..sub.V supplied to the gate electrodes 5, the channel potentials under the transfer gates 4 flow back and forth between .phi..sub.T (L) and .phi..sub.T (H) while those under the vertical CCDs flow back and forth between .phi..sub.C (L) and .phi..sub.C (H). During this period, the photodetectors 70 are at potentials lower than .phi..sub.T (H), and hence no signal charge Q.sub.sig is read on the gates of the vertical CCDs.
In the reading state a shown in FIG. 1B, the potentials of the gate electrodes 5 are at "HH" levels higher than the "H" levels in the storage state, and hence the signal charges stored in the photodetectors 70 are read in the gates of the vertical CCDs.
"A Zigzag-Transfer CCD Imager" by H. Matsumoto et al., ISSCC "Digest of Technical Papers" 1978, pp. 28-29 discloses a solid state image sensing device which controls transfer gates and the gates of CCDs by common gate electrodes similarly to the aforementioned solid state image sensing device. In the said solid state image sensing device, potential difference between the transfer gates and the gates of the CCDs is realized by changing thickness of an oxide film.
In the conventional solid state image sensing device employing the CCDs as hereinabove described, the threshold voltage of the transfer gates for controlling reading of signal charges must be set at such a level that no signal charge is read in states other than the reading state. In order to form transfer gates having such threshold voltage, however, it has generally been necessary to correctly register the masks and selectively implant ions into regions for forming the transfer gates. Thus, the conventional solid state image sensing device has been deteriorated in performance by misregistration of the masks. In addition, it has been required to further improve accuracy of registration of the masks in order to miniaturize the solid state image sensing device.